DM9161CI DAVICOM [Davicom Semiconductor, Inc.], DM9161CI Datasheet - Page 16

• Manufacturer Part Number: DM9161CI
• Description: Industrial-Temperature 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

7.2 100Base-TX Operation
The 100Base-TX transmitter receives 4-bit nibble data
clocked in at 25MHz at the MII, and outputs a scrambled
5-bit encoded MLT-3 signal to the media at 100Mbps. The
on-chip clock circuit converts the 25MHz clock into a
125MHz clock for internal use.
The IEEE 802.3u specification defines the Media
Independent Interface. The interface specification defines
a dedicated receive data bus and a dedicated transmit
data bus.
18
Signals
MII
Interface/
Control
MII
Encoder
Decoder
4B/5B
4B/5B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Register
Scrambler
Alignment
Code-
group
25M OSCI
TX CGM
to Serial
Descrambler
Parallel
Detection
Collision
Figure 7-3
25M CLK
NRZI
NRZ
to
Serial to
Parallel
Digital
Logic
These two busses include various controls and signal
indications that facilitate data transfers between the
DM9161CI and the Reconciliation layer.
7.2.1 100Base-TX Transmit
The 100Base-TX transmitter consists of the functional
blocks shown in figure 7-3. The 100Base-TX transmit
section converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125, a million symbols per
second serial data stream.
Carrier
Sense
NRZI to
MLT-3
125M CLK
NRZI
NRZ
to
LED1-4#
Negotiation
Rise/Fall
MLT-3
Driver
Driver
Time
LED
Auto-
CTL
CRM
RX
MLT-3 to
10BASE-T
NRZI
Module
AutoMDIX
RX
TX
Adaptive
EQ
Version: DM9161CI-DS-F01
DM9161CI
100TXD+/-
RXI+/-
RXI+/-
10TXD+/-
February 22, 2012
Final