LUCL9310AP-D AGERE [Agere Systems], LUCL9310AP-D Datasheet - Page 27

• Manufacturer Part Number: LUCL9310AP-D
• Description: Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device
• Manufacturer: AGERE [Agere Systems]

July 2001
Agere Systems Inc.
Electrical Characteristics
Logic Inputs and Outputs, V
Table 13. Logic Inputs and Outputs
Timing Requirements
Table 14. Timing Requirements
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3.
The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision out-
put is not controlled by the LATCH control input.
Input Voltages:
Input Current:
Output Voltages (CMOS):
Minimum Setup Time from B0, B1, B2, B3 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2, B3
Low Level
High Level
Low Level (V
High Level (V
Low Level (V
High Level (V
DD
DD
DD
DD
= 5.25 V, V
= 4.75 V, I
= 5.25 V, V
= 4.75 V, I
Parameter
OL
Parameter
OH
I
I
= 0.4 V)
LATCH
B0, B1,
B2, B3
= 2.4 V)
= 180 A)
= –20 A)
DD
(continued)
= 5.0 V
Full-Feature SLIC, Ringing Relay, and Test Access Device
Figure 4. Timing Requirements
t
SU
Symbol
SU
t
t
SU
HL
ns before LATCH goes low and held t
Symbol
t
HL
Min
200
V
V
V
V
50
I
I
IH
OH
IL
OL
IH
IL
–0.5
Typ
Min
2.0
2.4
—
—
—
—
0
Typ
0.4
2.4
0.2
—
—
—
Max
—
—
Max
V
±50
±50
V
0.7
0.4
DD
CC
HL
ns after
Unit
ns
ns
12-3526(F)
Unit
V
V
V
V
A
A
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