EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 77

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
8.2.29
Register
Address
81h
Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]
Read/
Write
R/W
The individual fan tach error event bits are defined as follows:
0=disable
1=enable.
See
Register 81h: TACH_PWM Association Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan
logic to determine when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a. if the current value in Current PWM Duty registers is 00h or
b. if the fan is disabled via the Fan Configuration Register.
Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below.
Notes:
■
■
Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
All TACH inputs must be associated with a PWM output. If the tach is not being driven by the
associated PWM output it should be configured to operate in Mode 1 and the associated TACH
interrupt must be disabled.
Figure 6.1 Interrupt Controlon page
Table 8.47 Register 81h: TACH_PWM Association Register
TACH_PWM Association
00
01
10
11
Register Name
Table 8.48 Bit Combinations
DATASHEET
(MSb)
Bit 7
T4H
27.
77
Bit 6
T4L
Bit 5
T3H
PWM Associated With Tachx
Bit 4
T3L
Bit 3
T2H
Reserved
PWM1
PWM2
PWM3
Bit 2
T2L
Bit 1
T1H
Revision 0.4 (04-04-05)
(LSb)
Bit 0
T1L
Default
Value
A4h