EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 60

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.4 (04-04-05)
8.2.9
Register
Address
41h
Note
Read/
Write
(See
2. If Start bit = '1'
a. All fan control and monitoring will be based on the current values in the registers. There is no need
b. Status bits may be set.
c. Setting the START bit to 1 does not prevent the limit and parameter registers from being written.
Note: Once programmed, the register values will be saved when start bit is reset to ‘0’.
Register 41h: Interrupt Status Register 1
R-C
Note 8.9
Note: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp)
The Interrupt Status Register 1 bits are automatically set by the device, if enabled, whenever the 2.5V,
Vccp, 3.3V, or 5V input voltages violate the limits set in the limit and parameter registers or when the
measured temperature violates the limits set in the limit and parameter registers for any of the three
thermal inputs.
This register holds a bit set until the event is read by software or until the individual enable bit is
cleared (see Note below). The contents of this register are cleared (set to 0) automatically by the
EMC6D103 after it is read by software, if the voltage or temperature no longer violates the limits set
in the limit and parameter registers. Once set, the Interrupt Status Register 1 bits remain set until a
read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no
longer violate the limits set in the limit and parameter registers. Note that clearing the group Temp,
Fan, or Volt enable bits or the global INTEN enable bit has no effect on the status bits. See
44-4Dh: Voltage Limit Registers on page 63
This register contains a bit that indicates that a bit is set in the other interrupt status register. If bit 7
is set, then a status bit is set in the Interrupt Status Register 2. Therefore, S/W can poll this register,
and only if bit 7 is set does the other register need to be read. This bit is cleared (set to 0) automatically
by the device if there are no bits set in Interrupt Status Registers 2.
This register is read only – a write to this register has no effect.
Note: Clearing the individual enable bits:
1. An interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt
2. If the individual enable bit is cleared while the associated status bit is 1, the status bit will be
8.9)
to preserve the default values after software has programmed these registers because no
monitoring or auto fan control will be done when Start bit = '0'.
enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement.
cleared when the associated reading register is updated. The reading registers only get updated
when the START bit is set to ‘1’. If the enable bit is cleared when the START bit is 0, the associated
interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register
is updated.
register at offset 82h. The individual enable bits for 5V, VCC, Vccp, and 2.5V are located in
the Interrupt Enable 1 register at offset 7Eh.
This register is cleared on a read if no events are active.
Table 8.14 Register 41h: Interrupt Status Register 1
Interrupt Status 1
Register Name
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
DATASHEET
(MSb)
Bit 7
INT2
60
Bit 6
and
D2
on page
Bit 5
AMB
Bit 4
64.
D1
Bit 3
5V
Bit 2
VCC
Bit 1
Vccp
SMSC EMC6D103
(LSb)
Bit 0
2.5V
Datasheet
Registers
Default
Value
00h