EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 74

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.4 (04-04-05)
AVG2
0
0
0
1
SFTR[7:5]
AVG1
This register contains the following bits:
Bit[0] Low-Power Mode Select
0= Sleep Mode (default)
1= Shutdown Mode
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] INT# Enable
0=Disables INT# pin output function (default)
1=Enables INT# pin output function
Bit[3] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted
results.
Bit [4] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause
unwanted results.
Bits [7:5]
The AVG[2:0] bits determine the amount of averaging for each of the six measurements that are
performed by the hardware monitor before the reading registers are updated
Decoder"). The AVG[2:0] bits are priority encoded where the most significant bit has highest priority.
For example, when the AVG2 bit is asserted, 32 averages will be performed for each measurement
before the reading registers are updated regardless of the state of the AVG[1:0] bits.
Note: The default for the AVG[2:0] bits is ‘010’b.
X
0
0
1
AVG0
AVG[2:0]
X
X
0
1
REM DIODE 1
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Table 8.43 AVG[2:0] Bit Decoder
128
16
16
32
DATASHEET
REM DIODE 2
74
128
16
16
32
AVERAGES PER READING
INTERNAL DIODE
16
32
8
1
(Table 8.43, "AVG[2:0] Bit
(+2.5V, +5V, +12V,
VCCP, AND VCC)
ALL VOLTAGE
READINGS
SMSC EMC6D103
16
32
8
1
Datasheet