EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 69

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
8.2.17
Register
Address
62h
63h
Read/
Write
R/W
R/W
Note: The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional
Register 62h, 63h: PWM Ramp Rate Control
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
The duty cycle will be set to the Minimum Fan Duty Cycle when the measured temperature falls below
the Temperature LIMIT register setting for the corresponding PWM.
Description of Ramp Rate Control bits:
If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature
spikes may be sampled by the part. The auto fan control logic calculates the PWM duty cycle for all
temperature readings. If Ramp Rate Control is disabled, the PWM output will jump or oscillate
between different PWM duty cycles causing the fan to suddenly change speeds, which creates
unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent the PWM output from
jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined ramp
rate.
Ramp Rate Control
The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time.
This period of time is programmable via the Ramp Rate Control bits. For a detailed description of the
Ramp Rate Control bits see
Rate Control Logic on page
Note:
■
■
■
■
RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
PWM 1 Ramp Rate Control
Table 8.29 Register Setting vs. Temperature Range (continued)
Table 8.30 Register 62h, 63h: Min/Off, PWM Ramp Rate Control
PWM 2, PWM 3 Ramp
entries, the PWM will go on full when the temp reaches the next integer value e.g., for 3.33,
PWM will be full on at (min. temp + 4).
Register Name
Rate Control
RAN[3:0]
1000
1001
1010
1011
1100
1101
0111
1110
1111
39.
Table
(MSb)
RR2E
Bit 7
RES
8.31. For a description of the Ramp Rate Control logic see
DATASHEET
RR2-2
Bit 6
RES
69
RR2-1
Bit 5
RES
RANGE (°C)
13.33
26.67
53.33
10
16
20
32
40
80
RR2-0
Bit 4
RES
RR1E
RR3E
Bit 3
RR1-2
RR3-2
Bit 2
RR1-1
RR3-1
Bit 1
Revision 0.4 (04-04-05)
RR1-0
RR3-0
(LSb)
Bit 0
Default
Value
E0h
00h
Ramp