SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 41

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

5.3.3.1
5.3.4
Datasheet
Summary of Serial Poll-Mode Service Requests
The major steps involved in a Poll-mode service-request/service-acknowledge sequence are:
Daisy-Chaining Service Requests with CD1400s
The CD1284 can be combined with other CD1284 or CD1400 devices to form systems with more
than two serial channels and one parallel channel. There are a number of ways that these can be
connected, but one way provides a more efficient service-request/service-acknowledge sequence.
This method allows the CD1284s and/or CD1400s to arbitrate between themselves. This mode
only works if hardware-activated service acknowledges are being utilized. The Fair Share
mechanism is not functional on the parallel channel service-request (SVCREQP*) outputs.
Therefore, two CD1284s can be daisy-chained if SVCREQP* and SVCACKP* are kept separate.
The serial channel requests and acknowledges are identical to those on the CD1400 so they can be
connected to the equivalent requests and acknowledges on the CD1284.
The CD1284 provides a means of daisy-chaining the service request and service acknowledgments
of two or more devices. This allows them to arbitrate and set priorities between themselves
regarding which one can post a particular type of service request. This is the Fair Share interrupt
scheme.
function.
All request outputs of a particular type from the two CD1284s (SVCREQR*, SVCREQT*, and
SVCREQM*) are wire-OR’ed together to form one combined request for each type; the
SVCREQP* of each is kept separate. This allows both devices to monitor the state of the others
output. All of t h e s e r i a l se r v ic e - a c k n ow le d g e i n p u ts (SVCACKR*, SVCACKT*, and
SVCACKM*) are connected together to form one acknowledge of each type. Note, the
SVCACKP* are driven individually. The DGRANT* input of the first CD1284 is connected to
ground; the DPASS* output of the first CD1284 drives the DGRANT* input of the second.
1. The CPU scans the SVRR periodically, checking the three least-significant bits. If any of them
2. Depending on which of the service-request bits is active, reads the appropriate interrupt
3. Performs a service routine.
4. Writes the original contents of the interrupt request register back with the most-significant two
are true (‘1’), a service request is active.
request register (RIR, TIR, or MIR) and copies the contents into the CAR.
bits cleared.
Figure 6 on page 42
IEEE 1284-Compatible Parallel Interface Controller — CD1284
illustrates the connection for two CD1284s to enable the Fair Share
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