SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 109

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.1.3
7.1.4
7.1.5
Datasheet
Register Name: GPDIR
Register Description: General-Purpose I/O Direction
Access: Read/Write
Register Name: GPIO
Register Description: General-Purpose I/O
Access: Read/Write
Register Name: MICR
Register Description: Modem Interrupting Channel
Access: Read/Write
Data 7
Dir 7
Bit 7
Bit 7
Bit 7
X
Secondly, a system programmer can use this register to indicate when the internal processor
completes reset procedures. This is done by a power-on reset (by the RESET* input) or a software
global reset (by the reset command in the CCR). Immediately after the reset operation begins, the
internal CPU clears the register. When complete, and the CD1284 is ready to accept host accesses,
the register is loaded with the revision code.
General-Purpose I/O Direction Register
General-Purpose I/O Register
This pair of registers enables access and control of the general-purpose I/O port. The general-
purpose I/O port provides a byte-wide general purpose set of signals that are individually direction
programmable.
The GPIO register accesses the data port on pins 53–60 (G[7:0]) with Data 0 accessing GP[0], etc.
The corresponding bit in the GPDIR register controls the direction of the associated signal; ‘1’
programs the signal as output and ‘0’ programs it as input. When writing to the GPIO register, ‘1’s
and ‘0’s are reflected in their true states on the pins that are programmed as outputs. When reading
from the GPIO register, bits programmed as inputs reflect the true state of the signal condition on
those bits; bits programmed as output reflect the previously set state.
Modem Interrupting Channel Register
The MICR, RISR, and TICR indicate the serial channel number that is currently being serviced by
an active acknowledge cycle (whether polled or interrupt). Bits 3:2 (C1 and C0) are only valid
during the context of a channel service routine; at any other time, their state is undefined. Host
system software uses these registers to determine the number of the channel that originated the
particular service request (receive, transmit, or modem). The format of these registers is the same
and the description is valid for each. The upper four bits and lower two bits are user-defined and
can be set to any value desired. When the register is read, these bits are presented as defined by the
user; C1 and C0 are set by the CD1284 to reflect the proper channel number.
Data 6
Bit 6
Dir 6
Bit 6
Bit 6
X
Data 5
Dir 5
Bit 5
Bit 5
Bit 5
X
IEEE 1284-Compatible Parallel Interface Controller — CD1284
Data 4
Dir 4
Bit 4
Bit 4
Bit 4
X
Data 3
Bit 3
Bit 3
Dir 3
Bit 3
C1
Data 2
Bit 2
Dir 2
Bit 2
Bit 2
C0
Data 1
Dir 1
Bit 1
Bit 1
Bit 1
8-Bit Hex Address: 46
8-Bit Hex Address: 71
X
8-Bit Hex Address: 70
Default Value: 00
Default Value: 00
Default Value: 00
Data 0
Bit 0
Bit 0
Dir 0
Bit 0
X
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