SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 114

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.2.1
7.2.2
114
Register Name: MISR
Register Description: Modem Interrupt Status
Access: Read only
Register Name: MIVR
Register Description: Modem Interrupt Vector
Access: Read only
DSRch
Bit 7
Bit 7
X
Bit
3:0
7
6
5
4
Virtual Registers — Serial
Modem Interrupt Status Register
The MISR provides the status regarding a modem service request. If the modem-signal change
detections (zero-to-one or one-to-zero transition) are enabled in MCOR1 or MCOR2, the change
causes a service request and the changed signal is flagged in this register.
Modem Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKM* is activated in
response to an active SVCREQM*. See
Data Set Ready Change: An enabled transition on the Data Set Ready signal causes this bit to be set and a
modem service request posted.
Clear To Send Change: An enabled transition on the Clear To Send signal causes this bit to be set and a
modem service request posted.
Ring Indicator Change: An enabled transition on the Ring Indicator signal causes this bit to be set and a
modem service request posted.
Carrier Detect Change: An enabled transition on the Carrier Detect signal causes this bit to be set and a
modem service request posted.
These read-only bits always return ‘0’.
CTSch
Bit 6
Bit 6
X
IT2
0
0
0
1
l
RIch
Bit 5
Bit 5
IT1
X
0
0
1
1
l
CDch
IT0
Bit 4
Bit 4
0
1
0
1
l
X
Section 7.4.6 on page 128
No modem interrupts.
Group 1: Modem signal change service request.
Invalid.
Description
Bit 3
Bit 3
0
X
Bit 2
Bit 2
IT2
0
Description
for more details on the LIVR.
Bit 1
Bit 1
8-Bit Hex Address: 4C
IT1
8-Bit Hex Address: 41
0
Default Value: 00
Default Value: 00
Datasheet
Bit 0
Bit 0
IT0
0