SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 157

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

8.3
8.3.1
Datasheet
Number
Timing
Table 27. Asynchronous Timing Reference Parameters (Sheet 1 of 2)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
Figure
Figure
20
22
22
22
22
22
22
22
22
22
22
23
23
21
21
21
24
24
25
25
27
22
25
25
27
AC Characteristics
Asynchronous Timing
Refer to the Figures 6-1 through 6-7 for the reference numbers in the following table.
RESET* low pulse width
Address setup time to CS* or DS*
R/W* setup time to CS* or DS*
Address hold time after CS*
R/W* hold time after CS*
DTACK* low to read data valid
DTACK* low from CS* or DS
Data Bus tristate after CS* or DS* high
CS* or DGRANT* high from DTACK* low
DTACK* inactive from CS* or DGRANT* and DS* high
DS* high pulse width
Write data valid from CS* and DS* low
Write data hold time after DS* high
Clock period (TCLK)
Clock low time
Clock high time
Propagation delay, DGRANT* and DS* to DPASS*
Setup time, SVCACK* to DS* and DGRANT*
Setup time, DMAACK* to rising edge of CLK
Hold time, read data after rising edge of CLK
Setup time, write data to rising edge of CLK
DTACK* active pull-up time
Data valid after falling edge of CLK (DMA read)
Hold time, DMAREQ* after DMAACK* falling edge,
last DMA cycle
1
1
1, 3
Parameter
IEEE 1284-Compatible Parallel Interface Controller — CD1284
4
2
0.3 T
0.3 T
2 T
40.0
MIN
10
10
10
10
10
10
10
10
0
0
0
0
0
0
CLK
CLK
CLK
4 T
1 CLK
see note 4
0.7 T
0.7 T
1T
MAX
CLK
1000
10
30
40
35
30
25
CLK
CLK
CLK
15
30
T
Unit
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
157