SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 148

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.8.4
7.8.5
7.8.6
148
Register Name: MDR
Register Description: Manual Data
Access: Read/Write
Register Name: NER
Register Description: Negotiation Enable
Access: Read/Write
Register Name: NSR
Register Description: Negotiation Status
Access: Read/Write
NegOK
Bit 7
Bit 7
Bit 7
0
Bit
7
6
5
4
3
2
1
0
Manual Data Register
This read/write register can read the state of the PD[7:0] signals in any mode. If the ManMd bit
(PCR[7]) and the MMDir and ManOE bits (PCR[1:0]) are set, then the value written into this
register is driven onto the PD[7:0] signals.
Negotiation Enable Register
Each bit set along with EICR (PCR[6]) allows the CD1284 to engage in IEEE STD 1284
negotiations and move into the corresponding protocol. It is assumed that the peripheral host
software responds to a request for slave ID and is able to send an ID string in any supported
protocol. In response to an ID request, the CD1284 does not provide a method of storing and
automatically sending an ID string. Note that the EPP protocol does not have provision for slave ID
requests.
Negotiation Status Register
The results of negotiation attempts are stored in this register.
Reserved: This read-only bit is always ‘0’.
Request Slave ID
Reserved: This bit must always be ‘0’.
EPP Mode Enable
Run Length Encoding in ECP Mode Enable
ECP Mode Enable
Reverse Byte Mode Enable
Reverse Nibble Mode Enable
NegFl
Bit 6
Bit 6
Bit 6
RID
HostTO
Bit 5
Bit 5
Bit 5
0
ImedTerm
Bit 4
Bit 4
EPP
Bit 4
8-bit Binary Data
Description
Bit 3
Bit 3
RLE
Bit 3
4-bit Negotiation Result Code
Bit 2
Bit 2
ECP
Bit 2
RVB
Bit 1
Bit 1
Bit 1
8-Bit Hex Address: 29
8-Bit Hex Address: 28
8-Bit Hex Address: 21
Default Value: 00
Default Value: 00
Default Value: 00
Datasheet
RVN
Bit 0
Bit 0
Bit 0