SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 138

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.7.4
7.7.5
138
Register Name: HRSR
Register Description: Holding Register Status
Access: Read only
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: Read/Write
HR1full
Bit 7
Bit 7
Bit
7:6
5:4
3:2
1
0
These resisters can be read through DMA acknowledge or PIO cycles, however, the DMABUF
registers can only be read when the DMAREQ* signal is active. If DMAREQ* is inactive, the
DMABUF registers will be empty. DMAfull (HRSR[3]) indicates if the DMABUF register is
empty when DMAREQ* is active.
Firmware Revision Code Holding Register Status Register
The HRSR is a read-only register that indicates current data pipeline status. This register is not
directly set to any particular value by a device reset, but reflects the current state of bits in other
registers.
Local Interrupt Vector Register
This read/write register can be initialized to any desired value and, when read in the normal context
(that is, not a service acknowledge context), the same value will be returned. The upper 5 bits are
copied into the appropriate vector register (MIVR, PIVR, TIVR, or RIVR) when the corresponding
SVCACK* signal is activated and an SVCREQ* of the same type is active. During this hardware-
activated service acknowledge read cycle, the appropriate vector register (MIVR, PIVR, TIVR, or
RIVR) is driven onto the data bus, DB[7:0].
Holding Register 1 Full and Holding Register 1 Tagged: These two bits indicate status of PFHR1. Bit 7
indicates that the register contains data; bit 6 indicates that the data is tagged. Bits 7 and 6 can be set
simultaneously.
Holding Register 2 Full and Holding Register 2 Tagged: These two bits indicate status of PFHR2. Bit 5
indicates that the register contains data; bit 4 indicates that the data is tagged. Bits 5 and 4 can be set
simultaneously.
DMA Buffer Full and DMA Buffer Empty: These two bits indicate status of the DMA transfer buffer (DMA
buffer). Bit 3 indicates that the register contains data; bit 2 indicates that it is empty.
DMA Active: When this bit is set, it indicates that the DMA handshake is active and a DMA service has been
requested but is not yet complete (DMAREQ* active – waiting for DMAACK*).
Count Not Zero: This bit indicates that the RLE counter is not zero, thus run-length encoding/decoding is in
progress.
HR1tag
Bit 6
Bit 6
User-Defined Bits
HR2full
Bit 5
Bit 5
HR2tag
Bit 4
Bit 4
Description
DMAfull
Bit 3
Bit 3
DMAmpty
Bit 2
Bit 2
IT2
DMAact
Bit 1
Bit 1
IT1
8-Bit Hex Address: 34
8-Bit Hex Address: 18
Default Value: 04
Default Value: 00
Datasheet
Ctnot0
Bit 0
Bit 0
IT0