SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 83

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

DMAACK*
DMAREQ*
DB[15:0]
Datasheet
NOTES:
DMAREQ*
DMAACK*
1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.
2. If DMAACK* is released after point ‘a,’ but before point ‘b’ (two rising CLK edges after the falling edge of DMAACK*), DB[15:0]
3. This
DB[15:0]
NOTE: The falling edge of DMAACK* is synchronized internally with the rising edge of the clock when
CLK
is released at t
data bus remains active until DMAACK* becomes inactive (point ‘c’).
Figure 22. Asynchronous DMA Read Cycle Timing
Figure 23. Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)
CLK
Figure 22
asynchronous timing is selected by PACR[1]. The data valid time can vary by as much as one full CLK
cycle depending on when DMAACK* falling edge occurs in relation to the CLK rising edge. The minimum
DMAACK* active time must be met to ensure that the data has become valid before the rising edge of
DMAACK*. The DMAACK* can be extended to any length, which extends the data valid hold time
accordingly. If t
tristates t
20
is still valid, however,
27
following the rising edge of CLK. If DMAACK* is held past this edge, it controls the release of DB[15:0]; the
after the third rising clock edge following the assertion of DMAACK*.
25
is not met and DMAACK* is deasserted in less than t
DMAACK* SYNCHRONIZED
Figure 23
HERE
t
t
19
24
SEE NOTE
t
illustrates a more robust timing.
26
t
25
IEEE 1284-Compatible Parallel Interface — CD1283
t
23
‘a’
VALID
MAY CHANGE
t
28
VALID
t
27
25
(MIN), then the data bus
t
29
SEE NOTE
‘b’
t
20
VALID
‘c’
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