SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 47

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

6.0
6.1
6.2
6.2.1
Datasheet
Programming
Overview
As shown in the register summary tables in
of a large array of registers. These registers control all aspects of device behavior. Most registers
are only modified once, during initialization, and rarely modified during normal operation. This
chapter discusses these aspects, as well as the methods of interacting with the CD1283 for parallel-
channel service requirements.
Initialization
To properly power-up a CD1283, several procedures must be completed. These include device
initialization, programming global functions, and setting port parameters. In most cases,
initialization routines are only executed once – during overall system boot-up.
these steps
Device Reset
The procedures that perform chip reset are normally executed after a power-up, system-wide reset.
The hardware reset control signal, RESET* causes the CD1284 to perform its own internal
initialization. If desired, the driver software can issue a full chip reset before chip initialization
begins. To accomplish this, perform the following steps.
1. Wait for RCR to contain ‘0x00’.
2. Set the AER ‘0x02’.
3. Write hexadecimal 81 (x’81) to the RCR.
4. Wait for the firmware revision code to be written into the GFRCR.
The contents of the RCR must be ‘0’ before the reset command is issued. This is required to
ensure that the device is ready to accept the new command. Since this is probably the first
command written to the CD1283 after power-on initialization, the RCR is likely to be ‘0’, but
it is recommended to always check the RCR before writing a new command.
This is the only time during normal operation that the AER is set to any value other than
‘0x00’. Again, this is required to maintain binary compatibility with the CD1284.
This command causes the CD1283 to perform a global reset. It causes the internal RISC
processor to begin execution from its power-up reset location. The results are the same as if
the RESET* input is activated. All internal interface registers are cleared, the FIFO is flushed,
and all channel operations are disabled.
Internal firmware uses this operation to flag completion of the reset procedure. After the reset
is issued, the GFRCR is one of the first registers cleared and it is the last one set before normal
runtime code execution begins. The initialization routine must wait for this register to become
non-zero before it begins any other programming of CD1284 registers. If the CPU is
sufficiently fast, it could begin testing the GFRCR before the MPU clears it. The assumption
could be made that the CD1284 has completed internal initialization when, in fact, it has not
even started. To avoid this error, the CPU should look for the GFRCR to change to ‘0’. It
should then look to the current revision code. Alternatively, the CPU can clear the GFRCR just
prior to issuing the global reset command and then poll for the correct revision code. This is
(Figure 15 on page 48
for a flow-chart step outline).
IEEE 1284-Compatible Parallel Interface — CD1283
Chapter
4.0, the CD1283 local CPU interface consists
Section 6.2.1
details
47