SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 38

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
5.5.6
5.5.7
38
DB[15:8]
DB[7:0]
Figure 8. FIFO Data Path Functional Diagram: Transmit
Manual Mode
Manual mode allows direct control of the five output control signals and the PD bus. It is not
intended for data transfers, but rather for advanced diagnostics. Enter Manual mode by setting the
ManMd bit (PCR[7]) when the interface is in Compatibility mode.
The MMDir bit (PCR[1]) sets the direction of the PD bus: 0 input; 1 output. When the MMDir
bit is set to ‘1’, data for the PD bus comes from the MDR. The ManOE bit controls the tristate
buffer on the PD bus: 0 floating; 1
are inputs, and the data can be read in the MDR.
Control Signals
Output signals are controlled by the OVR. The degree of control depends on the current mode. In
Manual mode, all five signals are under user control. In Compatible and EPP modes, only three
signals are available, the others are set by the state machine.
IVR, ZDR, ODR, and SSR monitor the four input signals. These four registers have a common
format. The IVR always shows the values of the four input pins. ZDR and ODR allow the user to
force interrupts on specific signal transitions. Bits set in the ZDR generate an interrupt, if the
specified signal changes from ‘1’ to ‘0’. Similarly, bits set in the ODR generate an interrupt if the
specified signal changes from ‘0’ to ‘1’. When both bits are set, interrupts are generated on either
transition. The SSR shows the status of signal changes according to ZDR and ODR. SSR shows
which signal changed. (It is necessary for the user to read the IVR to determine how the signal
changed.) The signal change interrupt is enabled with the SigCh bit (PCIER[4]).
STATUS
(TRANSMIT)
TAG BIT
PFSR
STATUS
TAG
driving. When MMDir is ‘0’, ManOE is ignored, PD[7:0]
TAG
FIFO (64 BYTES)
TAG (64 BITS)
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