SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 58

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.3.2
7.3.3
58
Register Name: DMABUF
Register Description: DMA Buffer Data high
Access: R/W
Register Name: DMABUF
Register Description: DMA Buffer Data low
Access: R/W
Register Name: HRSR
Register Description: Holding Status
Access: Read only
HR1full
Bit 15
Bit 7
Bit 7
DMA Buffer Data Register
This 16-bit data register is used to buffer DMA data transfers to and from the CD1283. Under
normal operating conditions, this register is only accessed during a DMA data transfer cycle. If
DMAbufWe (PFCR0) is set to ‘1’ and DMAdir (PFCR[5]) is set to ‘1’, 16-bit data can be
transferred from the host to the FIFO by directly writing to the DMABUF. The data automatically
moves forward into the FIFO through the Data Pipeline Holding registers. The user must ensure
that the FIFO has sufficient free space to accept the data before writing into the DMABUF.
The BYTESWAP pin determines the order of byte transfer from this register into the data pipeline.
If BYTESWAP is set to ‘1’, data transferred on DB[15:8] is the first byte transferred into the data
pipeline and DB[7:0] is transferred second. If BYTESWAP is set to ‘0’ this sequence is reversed.
The same applies during data read during DMA transfers: if BYTESWAP is set to ‘1’, data from
the data pipeline moves to the upper byte of DMABUF, the next byte moves into the lower byte.
Again, if BYTESWAP is set to ‘0’, this sequence is reversed.
These resisters can be read through DMA acknowledge or PIO cycles. However, the DMABUF
registers can only be read when the DMAREQ* signal is active. If DMAREQ* is inactive, the
DMABUF registers will be empty. DMAfull (HRSR[3]) indicates if the DMABUF register is
empty when DMAREQ* is inactive.
Holding Register Status Register
The HRSR is read-only and indicates current data pipeline status This register is not directly set to
any particular value at device reset, but reflects the current state of bits in other registers
HR1tag
Bit 14
Bit 6
Bit 6
HR2full
Bit 13
Bit 5
Bit 5
DMA Buffer Data High Byte
DMA Buffer Data Low Byte
HR2tag
Bit 12
Bit 4
Bit 4
DMAfull
Bit 11
Bit 3
Bit 3
DMAmpty
Bit 10
Bit 2
Bit 2
DMAact
Bit 9
Bit 1
Bit 1
8-Bit Hex Address: 30
8-Bit Hex Address: 34
8-Bit Hex Address: 30
Default Value: 00
Default Value: 04
Default Value: 00
Datasheet
Ctnot0
Bit 8
Bit 0
Bit 0