SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 68

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.4.3
7.4.4
68
Register Name: MDR
Register Description: Manual Data
Access: R/W
Register Name: NER
Register Description: Negotiation Enable
Access: R/W
Bit 7
Bit 7
0
Bit
7:4
Bit
3
2
1
0
7
6
5
4
3
2
1
0
Manual Data Register
This read/write register can read the state of the PD[7:0] signals in any mode. If the ManMd bit
(PCR[7])is set along with the MMDir and ManOE bits (PCR[1:0]), then the value written into this
register is driven onto the PD[7:0] signals.
Negotiation Enable Register
Each bit set along with E1284 (PCR[6]) allows the CD1284 to engage in IEEE STD 1284
negotiations and move into the corresponding protocol. It is assumed that the peripheral host
software responds to a request for slave ID and is able to send an ID string in any protocol that it
supports. In response to an ID request, the CD1284 does not provide a method of storing and
automatically sending an ID string. Note that the EPP protocol does not have provision for slave ID
requests.
These read-only bits are always ‘0’.
A1284
nInit: (active-low Init input)
HstBsy: (Host Busy)
HstClk: (Host Clock)
Reserved: This read-only bit is always ‘0’.
Request Slave ID
Reserved: This bit must always be ‘0’.
EPP Mode Enable
Run Length Encoding in ECP Mode Enable
ECP Mode Enable
Reverse Byte Mode Enable
Reverse Nibble Mode Enable
Bit 6
Bit 6
RID
Bit 5
Bit 5
0
Bit 4
EPP
Bit 4
8-Bit Binary Data
Description
Description
Bit 3
RLE
Bit 3
ECP
Bit 2
Bit 2
RVB
Bit 1
Bit 1
8-Bit Hex Address: 28
8-Bit Hex Address: 21
Default Value: 00
Default Value: 00
Datasheet
RVN
Bit 0
Bit 0