SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 56

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.2
7.2.1
7.2.2
56
Register Name: EOSRR
Register Description: End-of-Service Request
Access: Write only
Register Name: PIVR
Register Description: Parallel Interrupt Vector
Access: Read only
Table 10. PIVR[2:0] Encoding
Bit 7
Bit 7
IT2
X
0
Virtual Registers
The CD1283 has two operational contexts: a normal context that allows host access to most
registers and any channel, and a service-acknowledge context, allowing host access to some
registers specific to the channel requesting service. This special set of registers is called ‘virtual’
because they are only available to host access and are valid during this service-acknowledge
context; at all other times, their contents will be undefined and must not be written to by host
software.
The use of Virtual registers and context switching allows the CD1283 to maintain all channel-
specific information. The host need not make any changes to chip registers to access the registers
pertinent to the parallel channel.
The service-acknowledge context is entered in one of two ways: either through activation of the
SVCACKP* input pin (hardware activated), or through host software when the contents of any one
of PIR is copied into the AER by host software during a Poll-mode Acknowledge cycle (software-
activated). See
End-of-Service Request Register
The EOSRR is a ‘dummy’ location and is used to signal the end of a hardware-activated service-
acknowledge procedure, invoked by the activation of SVCACKP*. The data pattern written is a
‘don’t care’ value. Writing this location causes the CD1283 to perform its internal switch out of the
service-acknowledge context. This register is used only during a hardware-activated service
acknowledge and must not be written during Poll-mode operation.
Parallel Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKP* is activated in
response to an active SVCREQP*. See
Bit 6
Bit 6
User-Defined – Upper 5 Bits of LIVR
X
IT1
0
Chapter 5.0
Bit 5
Bit 5
X
IT0
0
for a discussion of the differences between these two modes.
Description
No active interrupt.
Bit 4
Bit 4
X
Section 7.3.5 on page 60
Bit 3
Bit 3
X
Bit 2
Bit 2
IT2
X
for more details on the LIVR.
Bit 1
Bit 1
IT1
8-Bit Hex Address: 60
8-Bit Hex Address: 40
X
Default Value: XX
Default Value: 00
Datasheet
Bit 0
Bit 0
IT0
X