SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 17

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Datasheet
SVCREQP*
SVCACKP*
DGRANT*
DPASS*
PD[7:0]
GP[7:0]
A_1284
nInit
HstBsy
HstClk
NOTE: The above four parallel handshake signals are driven by the master in an IEEE Std 1284 interface, and as such are
PerClk
PerBsy
AkDaRq
Xflag
nDatAv
Symbol
inputs to the CD1283. Their functions depend on the transfer protocol selected. Refer to the IEEE Std 1284-1994
document for protocol functions. (See
Pin No.
41–48
53–60
68
69
70
71
31
34
32
33
37
36
35
39
38
Type
OD
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
ACTIVE-LOW SERVICE REQUEST PARALLEL: This is an open-drain output and
must be tied to external V
vated by certain conditions on the parallel port (such as, negotiation changes, direction
changes, etc.). SVCREQP* is not activated by FIFO threshold, or FIFO full/empty con-
ditions (refer to
fully interrupt-driven system).
ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL: This input must not be driven
active except in response to a parallel service request presented by the device.
ACTIVE-LOW DAISY GRANT: This input is driven active during service acknowledge
cycles to enable the daisy-chain function. This input, when qualified with DS* and a
valid service acknowledge (SVCACKP*), activates the service acknowledge cycle.
ACTIVE-LOW DAISY PASS: This output is driven active during service acknowledge
cycles to enable the next device in the daisy-chain. It is driven active when no valid
service request exists and the service acknowledge input is active. In multiple CD1283
designs, this signal is normally connected to the DGRANT* input of the next device in
the chain.
PARALLEL PORT DATA LINES [7:0]: Bidirectional, depending on the protocol being
used, these signals are used to transfer data over the interface between the master
and slave.
GENERAL-PURPOSE I/O [7:0]: General-purpose input/output port data lines. These
signals are individually direction-programmable, acting as inputs or outputs. The
direction of each signal is controlled by the corresponding bit in the GPDIR register.
Control/status of the actual signals is provided through the GPIO register.
ACTIVE-HIGH 1284 ACTIVE INPUT: (SLCTIN* in Compatibility mode).
ACTIVE-LOW INIT SIGNAL: (INIT* in Compatibility mode).
ACTIVE-HIGH HOST BUSY SIGNAL: (AUTOFD* in Compatibility mode).
ACTIVE-LOW HOST CLOCK SIGNAL: (STROBE* in Compatibility mode).
ACTIVE-LOW PERIPHERAL CLOCK: (ACK* in Compatibility mode)
ACTIVE-HIGH PERIPHERAL BUSY: (BUSY in Compatibility mode)
ACKNOWLEDGE DATA REQUEST: (PERROR* in Compatibility mode)
EXTENSIBILITY FLAG: (SELECT in Compatibility mode)
ACTIVE-LOW DATA AVAILABLE SIGNAL: (FAULT* in Compatibility mode)
Chapter 10.0
Chapter 5.0
for ordering information.)
IEEE 1284-Compatible Parallel Interface — CD1283
CC
through a pull-up resistor. Note that this output is only acti-
for information on how to use DMAREQ* to implement a
Description (Sheet 2 of 3)
17