TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 85

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Facility Data Link
The FDL interface to the receive framer is illustrated in Figure 32.
Receive ANSI T1.403 Bit-Oriented Messages (BOM)
Lucent Technologies Inc.
Lucent Technologies Inc.
Transparent operation with pattern match. Enabling the FDL and setting registers FDL_PR9 bit 5 (FMATCH)
and FDL_PR9 bit 6 (FTM) to 1 forces the FDL to start storing data in the FDL receive FIFO (register FDL_SR4)
only after the programmable match character defined in register FDL_PR8 bit 0—bit 7 has been detected. The
match character and all subsequent bytes are placed into the FDL receive FIFO.
The receive FDL monitor will detect any of the ANSI T1.403 ESF bit-oriented messages (BOMs) and generate an
interrupt, enabled by register FDL_PR6 bit 7, upon detection. Register FDL_SR0 bit 7 (FRANSI) is set to 1 upon
detection of a valid BOM and then cleared when read.
The received ESF FDL bit-oriented messages are received in the form 111111110X
bit is received first). The bits designated as X are the defined ANSI ESF FDL code bits. These code bits are writ-
ten into the received ANSI FDL status register FDL_SR3 when the entire code is received.
The minimum number of times a valid code must be received before it is reported can be programmed from 1 to
10 using register FDL_PR0 bit 4—bit 7.
RECEIVE LINE
RECEIVE
FRAMER
DATA
Figure 32. Block Diagram for the Receive Facility Data Link Interface
(continued)
LOSS OF FRAME
ALIGNMENT
IDENTIFYING THE ESF
BIT-ORIENTED CODE
ONE 8-bit REGISTER
BIT-ORIENTED DATA
ANSI T1.403-1995
LINK MESSAGES
RFDL
MONITOR
RECEIVE FDL
EXTRACTER
DATA
MICROPROCESSOR INTERFACE
RFDLCK
FACILITY DATA
TRANSPARENT
RECEIVE
64 8-bit LOCATIONS
RECEIVE FACILITY
DATA LINK FIFO
TFRA08C13 OCTAL T1/E1 Framer
RECEIVE FACILITY
DATA LINK HDLC
0
X
1
X
2
X
3
X
4
X
5
0 (the left most
RFDLCK
RFDL
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