TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 162
TFRA08C13-DB
Manufacturer Part Number
TFRA08C13-DB
Description
TFRA08C13 OCTAL T1/E1 Framer
Manufacturer
AGERE [Agere Systems]
Datasheet
1.TFRA08C13-DB.pdf
(188 pages)
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
CHI Common Control Register (FRM_PR46)
This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex).
Table 151. CHI Common Control Register (FRM_PR46) (Y8E)
CHI Transmit Control Register (FRM_PR47)
The default value of this register is 00 (hex).
Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F)
CHI Receive Control Register (FRM_PR48)
The default value of this register is 00 (hex).
Table 153. CHI Receive Control Register (FRM_PR48) (Y90)
162
0—2
4—6
0—5
0—5
Bit
Bit
Bit
3
7
6
7
6
7
RBYOFF0—
TBYOFF0—
RBYOFF5
TBYOFF5
ROFF0—
TOFF0—
Symbol
Symbol
Symbol
ROFF2
TOFF2
RCE
TCE
RFE
TFE
—
—
Transmit Byte Offset. Combined with FRM_PR65 bit 0 (TBYOFF6), these 6 bits define
the byte offset from CHIFS to the beginning of the next transmit CHI frame on
TCHIDATA.
Transmitter Clock Edge. A 1 (0) enables the rising (falling) edge of CHICK to clock out
data on TCHIDATA.
Reserved. Write to 0
Receiver Byte Offset. Combined with FRM_PR66 bit 0 (RBYOFF6), these 6 bits define
the byte offset from CHIFS to the beginning of the next receive CHI frame on RCHIDATA.
Receiver Clock Edge. A 1 (0) enables the rising (falling) edge of CHICK to latch data
on RCHIDATA.
Reserved. Write to 0
Transmit CHI Bit Offset. These 3 bits define the bit offset from CHIFS for each transmit
time slot. The offset is the number of CHICK clock periods by which the first bit is
delayed from TCHIFS.
Transmit Frame Clock Edge. A 0 (1) enables the falling (rising) edge of CHICK to latch
in the frame synchronization signal, CHIFS.
Receive CHI Bit Offset. These 3 bits define the bit offset from CHIFS for each received
time slot. The offset is the number of CHICK clock periods by which the first bit is
delayed from RCHIFS.
Received Frame Clock Edge. A 0 (1) enables the falling (rising) edge of CHICK to latch
in the frame synchronization signal, CHIFS.
(continued)
Description
Description
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000
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