TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 69

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Alarms and Performance Monitoring
Table 28. Alarm Indication Signal Conditions
* After a reset, the read and write pointers of the receive path elastic store will be set to a known state.
T1
CEPT ETSI
CEPT ITU
The SLIP condition (FRM_SR3 bit 6 and bit 7). SLIP is defined as the state in which the receive elastic store
buffer’s write address pointer from the receive framer and the read address pointer from the transmit concentra-
tion highway interface are equal
— The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (CHICK)
— The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (CHICK) monitoring circuit
The loss of framer receive clock (LORLCK, pin G23). The LORLCK alarm is asserted high when an interval of
250 ms has expired with no transition of RLCK (pin see Table 2. Pin Descriptions) detected. The alarm is dis-
abled on the first transition of RLCK. Bit 0—bit 2 of global register 8 (GREG8) determine which framer sources
the LORLCK pin (see Table 69 Interrupt Status Register (FRM_SR0) (Y00)).
The loss of PLL clock (LOPLLCK, pin F25). LOPLLCK alarm is asserted high when an interval of 250 ms has
expired with no transition of PLLCK (pin see Table 2 . Pin Descriptions) detected. The alarm is disabled 250 µs
after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 26. Bit 0—bit 2 of global register 8
(GREG8) determine which framer sources the LOPLLCK pin (see Table 69).
Framing Format
monitoring circuit detects a state of overflow caused by RLCK and CHICK being out of phase-lock and the
period of the received frame being less than that of the system frame. One system frame is deleted.
detects a state of underflow caused by RLCK and CHICK being out of phase-lock and the period of the
received frame being greater than that of the system frame. One system frame is repeated.
LOPLLCK
PLLCK
CHICK
Loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of
As described in ETSI ETS 300 233: May 1994, Section 8.2.2.4, loss of frame alignment
As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of
two consecutive double frame periods (386 bits).
occurs and the framer receives a 512 bit period containing two or less binary zeros. This
is enabled by setting register FRM_PR10 bit 1 to 0.
two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive
double frame periods contains three or more zeros or frame alignment signal (FAS) has
been found. This is enabled by setting register FRM_PR10 bit 1 to 1.
Figure 26. Timing for Generation of LOPLLCK (Pin F25)
*
.
250
(continued)
Remote Frame Alarm Format
s
TFRA08C13 OCTAL T1/E1 Framer
250
s
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