TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 58

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
CEPT Time Slot 0 FAS/NOT FAS Control
Bits
The receive Sa data is present at the following:
58
58
The CHI system interface if register FRM_PR29 bit
7—bit 5 are set to 001 (binary). This option requires
the received system data (RCHIDATA) to maintain a
biframe alignment pattern where (1) frames contain-
ing Sa bit information have bit 2 of time slot 0 in the
binary 1 state and (2) these NOT FAS frames are fol-
lowed by frames not containing Sa bit information,
the FAS frames, which have bit 2 of time slot 0 in the
binary 0 state. This ensures the proper alignment of
the Sa received system data to the transmit line Sa
data. Whenever this requirement is not met by the
system, the transmit framer will enter a loss of
biframe alignment condition indicated in the status
register, FRM_SR1 bit 4, and then search for the pat-
tern. In the loss of biframe alignment state, transmit-
ted line data is corrupted (only when the system
interface is sourcing Sa or Si data). When the trans-
mit framer locates a new biframe alignment pattern,
an indication is given in the status registers and the
transmit framer resumes normal operations.
The Sa received stack, registers FRM_SR54—
FRM_SR63, if the TFRA08C13 is programmed in the
Sa stack mode.
The system transmit interface.
RFDLCK
TFDLCK
RFDL
TFDL
(continued)
Figure 15. Facility Data Link Access Timing of the Transmit and Receive Framer Sections
in the CEPT Mode
t11
t8
t10
t9
t9
The status of the received Sa bits and the received Sa
stack is available in status register FRM_SR4. The
transmit and receive Sa bit for the FDL can be selected
by setting register FRM_PR43 bit 0—bit 2 as shown in
Table 148.
Sa Facility Data Link Access
The data link interface may be used to source one of
the Sa bits. Access is controlled by registers
FRM_PR29, FRM_PR30, and FRM_PR43, see NOT
FAS Sa-Bit Sources on page 57. The receive Sa data is
always present at the receive facility data link output
pin, RFDL, along with a valid clock signal at the receive
facility clock output pin, RFDLCK. During a loss of
frame alignment (LFA) state, the RFDL signal is forced
to a 1 state while RFDLCK continues to toggle on the
previous frame alignment. When basic frame alignment
is found, RFDL is as received from the selected receive
Sa bit position and RFDLCK is forced (if necessary) to
the new alignment. The data rate for this access mode
is 4 kHz. The access timing for the transmit and receive
facility data is illustrated in Figure 15 below. During loss
of receive clock (LOFRMRLCK), RFDL and RFDLCK
are frozen in a state at the point of the LOFRMRLCK
being asserted.
t8: TFDLCK CYCLE = 250 s
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10: RFDLCK CYCLE = 250 s
t11: RFDLCK TO RFDL DELAY = 40 ns
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000
5-3910(F).dr.1