TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 105

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Concentration Highway Interface
Figure 42 and Figure 43 illustrate the CHI timing.
Note: For case illustrated, RFE = 0, and RCE = 0.
Note: For case illustrated, TFE = 0 and TCE = 0.
JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module,
and system testing. The key aspects of BS are as fol-
lows:
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Testing the connections between ICs on a particular
board.
Observation of signals to the IC pins during normal
operating functions.
Controlling the built-in-self-test (BIST) of an IC.
TFRA08C13 does not support BS-BIST.
RCHIDATA
TCHIDATA
CHICLK
CHICLK
CHIFS
CHIFS
t15S
t14S
t14S
Figure 43. Transmit CHI (TCHIDATA) Timing
Figure 42. Receive CHI (RCHIDATA) Timing
(continued)
t15H
t19
t14H
t14H
Designed according to the IEEE Std. 1149.1-1990
standard, the BS test logic consists of a defined
interface: the test access port (TAP). The TAP is made
up of four signal pins assigned solely for test purposes.
The fifth test pin ensures that the test logic is initialized
asynchronously. The BS test logic also comprises a 16-
state TAP controller, an instruction register with a
decoder, and several test data registers (BS register,
BYPASS register, and IDCODE register). The main
component is the BS register that links all the chip pins
to a shift register by means of special logic cells. The
test logic is designed in such a way that it is operated
independently of the application logic of the
TFRA08C13 (the mode multiplexer of the BS output
cells may be shared). Figure 44 illustrates the block
diagram of the TFRA08C13’s BS test logic.
t14S: CHIFS SETUP = 35 ns min
t14H: CHIFS HOLD = 45 ns min
t19: CHICK TO TCHIDATA DELAY = 25 ns max
TFRA08C13 OCTAL T1/E1 Framer
t14S: CHIFS SETUP = 30 ns min
t14H: CHIFS HOLD = 45 ns min
t15S: RCHIDATA SETUP = 25 ns min
t15S: RCHIDATA HOLD = 25 ns min
5-3916(F).d
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