TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 155

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Framer Register Architecture
Table 140. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX
Sa4—Sa8 Control Register (FRM_PR30)
In conjunction with FRM_PR29 bit 5—bit 7, these bits define the source of the individual Sa4—Sa8 bits. The
default value of this register is 00 (hex).
Table 141. Sa4—Sa8 Control Register (FRM_PR30) (Y7E)
(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
SaS7
0—4
5—6
Bit
7
1
1
1
0
0
0
TESa4—TESa8
SaS6
0
0
1
1
0
0
Symbol
TDNF
—
SaS5
0
1
x
x
1
0
A single Sa bit, selected in register FRM_PR43, is sourced from either the external
transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-
HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced by this register
bit 0—bit 4 if enabled in register FRM_PR30, or transparently from the system inter-
face*.
A single Sa bit, selected in register FRM_PR43, is sourced from either the external
transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-
HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are transmitted transpar-
ently from the system interface*.
A single Sa bit, selected in register FRM_PR43, is sourced from either the external
transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDL-
HDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced from the trans-
mit Sa stack registers (FRM_PR31—FRM_PR40) if enabled in register FRM_PR30,
or transparently from the system interface*.
SLC -96 Mode. Transmit SLC -96 stack and the SLC -96 interrupts are enabled. The
SLC -96 FDL bits are sourced from the transmit SLC -96 stack, registers FRM_PR31—
FRM_PR40.
CEPT Mode. Transmit Sa stack and the Sa interrupts are enabled. The Sa bits are
sourced from the transmit Sa stack (FRM_PR31—FRM_PR40) if enabled in register
FRM_PR30, or transparently from the system interface*.
Sa[4:8] bits are transmitted from the system interface transparently through the
framer*.
Sa[4:8] bits are sourced by bit 0—bit 4 of this register if enabled in register
FRM_PR30, or transparently from the system interface*.
Transparent Enable Sa4—Sa8 Bit Mask. A 1 enables the transmission of the cor-
responding Sa bits from the Sa source register (FRM_PR29 bit 0—bit 4) or from the
transmit Sa stack. A 0 allows the corresponding Sa bit to be transmitted transpar-
ently from the system interface.
Reserved. Write to 0.
Transmit Double NOT FAS System Time Slot. A 0 enables the transmission of the
FAS and NOT FAS on the TCHIDATA interface. A 1 enables the NOT FAS to be
transmitted twice on the TCHIDATA interface, and the received time slot 0 from the
RCHIDATA is assumed to carry NOT FAS data that is repeated twice.
(continued)
Description
Function
TFRA08C13 OCTAL T1/E1 Framer
155