TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 146

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
Errored Second Threshold Register (FRM_PR11)
This register defines the errored event threshold for an errored second (ES). A one-second interval with errors less
than the ES threshold value will not be detected as an errored second. Programming 00 (hex) into this register dis-
ables the errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value
of this register is 00 (hex).
Table 120. Errored Second Threshold Register (FRM_PR11) (Y6B)
Severely Errored Second Threshold Register (FRM_PR12—FRM_PR13)
This 16-bit register defines the errored event threshold for a severely errored second (SES). A one-second interval
with errors less than the SES threshold value is not a severely errored second. Programming 00 (hex) into these
two registers disables the severely errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and
bit 7 = 0. The default value of these registers is 00 (hex).
Table 121. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) (Y6C—Y6D)
ET1 Errored Event Enable Register (FRM_PR14)
These bits enable the errored events used to determine errored and severely errored seconds at the local ET inter-
face. ETSLIP , ETAIS, ETLMFA, and ETLFA are the SLIP , AIS, LMFA, and LFA errored events, respectively, as
referred to the local ET interface. A 1 in the bit position enables the corresponding errored event. The default value
of this register is 00 (hex).
Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E)
ET1 Remote End Errored Event Enable Register
These bits enable the errored events used to determine errored and severely errored seconds at the ET's remote
end interface. ETRESa6-F , ETRESa6-E , ETRESa6-8 , ETRERFA , ETRESLIP , ETREAIS , ETRELMFA , and ETRELFA
are the Sa6-F , Sa6-E , Sa6-8 , RFA , SLIP , AIS , LMFA , and LFA errored events, respectively, as referred to the ET
remote end interface. A 1 in the bit position enables the corresponding errored event. The default value of this reg-
ister is 00 (hex).
Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F)
* One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.
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FRM_PR15 ETRESa6-F ETRESa6-E ETRESa6-8 ETRERFA ETRESLIP ETREAIS ETRELMFA ETRELFA
FRM_PR12
FRM_PR13
FRM_PR11
FRM_PR14
Register
Register
Register
Register
SEST15—SEST8 SES MSB Threshold Register.
SEST7—SEST0
Bit 7
EST7—EST0
Bit 7
0
Symbol
Symbol
Bit 6
Bit 6
0
SES LSB Threshold Register.
ES Threshold Register.
(continued)
Bit 5
Bit 5
0
*
(FRM_PR15)
Bit 4
Bit 4
0
ETSLIP
Bit 3
Description
Description
Bit 3
ETAIS
Bit 2
Bit 2
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
ETLMFA
Bit 1
Bit 1
October 2000
ETLFA
Bit 0
Bit 0