S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 70

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 



LDD
Operation:
Description:
Example:

dst
A,@HL
The contents of a data memory location are loaded into the accumulator, and the contents of the
register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is
0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not
affected.
A,@HL
In this example, assume that register pair HL contains 20H and internal RAM location 20H
contains the value 0FH:
LD
LDD
JPS
JPS
The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and
instruction 'JPS YYY' is executed.
Operand
Operand
HL,#20H
A,@HL
XXX
YYY
Load indirect data memory contents to A; decrement
register L contents and skip on borrow
1
0
0
Binary Code
Operation Summary
0
; A
; Skip
; H
1

0
(HL) and L
2H and L
1
1
0FH
A
skip if L = 0FH
L-1
(HL), then L
Operation Notation
Bytes
1
L-1;

 
Cycles
2 + S