S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 54

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 



IDLE
Operation:
Description:
Example:


IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of
the power control register (PCON). After an IDLE instruction has been executed, peripheral hard-
ware remains operative.
In application programs, an IDLE instruction must be immediately followed by at least three NOP
instructions. This ensures an adequate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructions are not used after IDLE instruction,
leakage current could be flown because of the floating state in the internal bus.
The instruction sequence
IDLE
NOP
NOP
NOP
sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions
provide the necessary timing delay for clock stabilization before the next instruction in the program
sequence is executed.
Operand
Operand
-
-


Engage CPU idle mode
1
1
1
0
1
1
Binary Code
Operation Summary
1
0
1
0
1
0
1
1
1
1
PCON.2
Operation Notation
1
Bytes
2

 
Cycles
2