S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 55

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 
 
INCS
Operation:
Description:
Example:
dst
R
DA
@HL
RRb
The instruction INCS increments the value of the destination operand by one. An original value of
0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry
flag value is unaffected.
R
DA
@HL
RRb
Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The
instruction sequence
INCS
INCS
INCS
leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a
carry occurred, the second instruction is skipped. The carry flag value remains unchanged.
Operand
Operand
@HL
HL
@HL
Increment register (R); skip on carry
Increment direct data memory; skip on carry
Increment indirect data memory; skip on carry
Increment register pair (RRb); skip on carry
a7
0
1
1
0
1
a6
1
1
1
1
0
a5
0
0
0
1
0
Binary Code
Operation Summary
a4
1
0
1
0
0

; Skip
; 7EH
; 7EH
a3
1
1
1
0
0
a2
r2
r2
0
1
0
"0"
"1"
a1
r1
r1
1
0
1
a0
r0
0
1
0
0
R
DA
(HL)
RRb
R + 1; skip on carry
DA + 1; skip on carry
(HL) + 1; skip on carry
Operation Notation
RRb + 1; skip on carry

 


Bytes
1
2
2
1
Cycles
1 + S
2 + S
2 + S
1 + S