S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 67

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 

LDB
Examples:

(Continued)
1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction
2. The P1 address is FF1H and the L register contains the value 1H (0001B). The address
3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for
4. The following instruction sequence sets the carry flag and the loads the "1" data value to the
5. The P1 address is FF1H and L = 01H (0001B). The address (memb.7-2) is 111100B and (L.3-
6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit
clears the carry flag to logic zero.
LDB
(memb.7-2) is 111100B and (L.3-2) is 00B. The resulting address is 11110000B or FF0H and
P0 is addressed. The bit value (L.1-0) is specified as 01B (bit 1).
LD
LDB
FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is
3. Therefore, @H+FLAG = 20H.3.
FLAG
LD
LDB
output pin P1.0, setting it to output mode:
SCF
LDB
2) is 00B. The resulting address, 11110000B specifies P0. The bit value (L.1-0) is specified as
01B (bit 1). Therefore, P1.@L = P0.1.
SCF
LD
LDB
value is 3, @H+FLAG = 20H.3:
FLAG
RCF
LD
LDB


C,P1.0
L,#0001B
C,P1.@L
EQU
H,#2H
C,@H+FLAG
P1.0,C
L,# 0001B
P1.@L,C
EQU
H,#2H
@H+FLAG,C
20H.3
20H.3
; P1.@L specifies P0.1 and C
; P1.@L specifies P0.1
; C
; C
; P1.0
; C
; P0.1
; C
; FLAG(20H.3)
FLAG (20H.3)
"1"
"1"
"0"
"1"
"1"
"0"

 


P0.1