ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 86

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.7
The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the
system clock speed at 100 MHz.
Note 1:
RAM_DATA[63:0] Output Valid
Delay
RAM_RW/RAM_ADDR[19:0]
Delay
RAM_BW[7:0]# Delay
RAM_DATA[63:0] Setup Time
RAM_DATA[63:0] Hold Time
RAM_PARITY[7:0] Output Valid
Delay
RAM_PARITY[7:0] Setup Time
RAM_PARITY[7:0] Hold Time
A1 - READ
A2 - WRITE
A3 - WRITE
A4 - READ
A5 - READ
A6 - WRITE
A7 - READ
A8 - WRITE
External Memory Interface Timing
M_MDIO
Must be capable of driving TWO separate RAM loads simultaneously.
RAM_PARITY[7:0]
RAM_ADDR[19:0]
M_MDC
RAM_DATA[63:0]
RAM_BW[7:0]
Parameter
RAM_RW
SCLK
Figure 40 - Management Interface Timing for Ethernet Port - Write
n
Phase 1
BW1
Figure 41 - External RAM Read and Write Timing
A1
Table 38 - External Memory Timing
Symbol
t
t
t
RAV
RAV
RBW
t
t
Phase 2
t
t
t
t
t
t
t
RBW
RDV
RDS
RDH
RAV
RPV
RPS
RPS
MD
BW2
A2
t
t
RPS
RDS
Zarlink Semiconductor Inc.
ZL50110/11/14
t
t
t
RDH
Phase 3
RPH
MP
P(A1)
BW3
D(A1)
Min.
A3
0.5
0.5
2
2
-
-
-
-
86
Phase 4
Q(A2)
P(A2)
BW4
A4
t
Typ.
t
RPV
RDV
-
-
-
-
-
-
-
-
Phase 5
Q(A3)
P(A3)
BW5
A5
t
RDS
Max.
4
4
4
4
-
-
-
-
t
RDH
Phase 6
P(A4)
BW6
D(A4)
A6
Units
t
t
ns
ns
ns
ns
ns
ns
ns
ns
RAV
RAV
Phase 7
P(A5)
BW7
D(A5)
A7
Load C
Load C
Note 1
Load C
Load C
Phase 8
t
t
Q(A6)
P(A6)
RDV
RPV
BW8
A8
Data Sheet
Notes
L
L
L
L
= 30 pF
= 30 pF
= 30 pF
= 30 pF