ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 42

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.7
3.7.1
All Administration, Control and Test Interface signals are 5 V tolerant.
3.7.2
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
GPIO[15:0]
TEST_MODE[2:0]
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
Test Facilities
Signal
Signal
Administration, Control and Test Interface
JTAG Interface
Table 16 - Administration/Control Interface Package Ball Definition
I/O
ID/
OT
I D
I/O
I U
I U
I U
O
I
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[2]
[1]
[0]
AE7
AD8
AA10
AF7
AC9
Table 17 - JTAG Interface Package Ball Definition
AA4
AB3
AC2
AC1
AB2
Y4
W5
AA3
AF6
AB9
AC8
Package Balls
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
42
AA2
Y3
AB1
Y2
W4
V5
AA1
W3
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at startup or reset for memory TDL setup.
See the ZL50110/11/14 Programmers Model
for more details. Recommend 5 kohm
pulldown on these signals.
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
JTAG Reset. Asynchronous reset. In normal
operation this pin should be pulled low.
Recommend external pull-down.
JTAG Clock - maximum frequency is
25MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low. Recommend external pull-down.
JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG test data input. Synchronous to
JTAG_TCK.
JTAG test data output. Synchronous to
JTAG_TCK.
Description
Description
Data Sheet