ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 79

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.5
11.6
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
11.6.1
TDM_CLKiP High / Low
Pulsewidth
TDM_CLKiS High / Low
Pulsewidth
TXCLK period
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
TXCLK to TXEN active delay
(TXCLK rising edge)
PAC Interface Timing
Packet Interface Timing
TDM_RXDATA
TDM_TXDATA
TDM_RXCLK
TDM_TXCLK
MII Transmit Timing
Parameter
Parameter
Figure 32 - TDM-LIU Structured Transmission/Reception
Table 32 - MII Transmit Timing - 100 Mbps
Symbol
Table 31 - PAC Timing Specification
t
t
t
t
t
CLO
t
t
CHI
Symbol
CC
CR
CF
DV
EV
t
t
CPP
CSP
t
Zarlink Semiconductor Inc.
S
ZL50110/11/14
Min.
14
14
1
1
Min.
-
-
-
10
10
t
t
CRP
CTP
79
100 Mbps
Typ.
Typ.
40
-
-
t
t
t
-
-
-
-
-
-
CTH
CRH
PD
t
H
Max.
-
-
Max.
26
26
25
25
5
5
-
t
t
CRL
CTL
Units
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
Load = 25 pF
Load = 25 pF
Data Sheet
Notes
Notes