ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 63
ZL50110
Manufacturer Part Number
ZL50110
Description
128, 256 and 1024 Channel CESoP Processors
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50110.pdf
(103 pages)
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7.8
The JTAG interface is used to access the boundary scan logic for board level production testing.
7.9
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7.10
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Direct connection to PowerQUICC™ II (MPC8260) host processor and associated memory, but can
support other processors with appropriate glue logic
TDM Framers and/or Line Interface Units
Ethernet PHY for each MAC port
Optional ZBT-SRAM for extended packet memory buffer depth
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
3.3 V I/O Supply rail with 5 V tolerance
1.8 V Core Supply rail
Fully compatible with MT90880/1/2/3 Zarlink product line
JTAG Interface and Board Level Test Features
External Component Requirements
Miscellaneous Features
SCLK
V
RST
DD
<0.5 V
DC
Figure 23 - Powering Up the ZL50110/11/14
Zarlink Semiconductor Inc.
10 ns
ZL50110/11/14
63
> 100 µs
Core supply (1.8 V)
I/O supply (3.3 V)
Data Sheet
t
t
t
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