ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 100

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15.0
API
ATM
CDP
CESoP
CESoPSN Circuit Emulation Services over Packet Switched Networks (draft-ietf-pwe3-cesopsn)
CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream.
CPU
DMA
DPLL
DSP
GMII
H.100/H.110 High capacity TDM backplane standards
H-MVIP
IA
IETF
IP
JTAG
L2TP
LAN
LIU
MAC
MEF
MFA
MII
MIB
MPLS
MTIE
MVIP
OC3
PDH
PLL
PRS
PRX
Glossary
Application Program Interface
Asynchronous Transfer Mode
Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices)
Circuit Emulation Services over Packet
Central Processing Unit
Direct Memory Access
Digital Phase Locked Loop
Digital Signal Processor
Gigabit Media Independent Interface
High-performance Multi-Vendor Integration Protocol (a TDM bus standard)
Implementation Agreement
Internet Engineering Task Force
Internet Protocol (version 4, RFC 791, version 6, RFC 2460)
Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test
facility)
Layer 2 Tunneling Protocol (RFC 2661)
Local Area Network
Line Interface Unit
Media Access Control
Metro Ethernet Forum
MPLS and Frame Relay Alliance
Media Independent Interface
Management Information Base
Multi Protocol Label Switching
Maximum Time Interval Error
Multi-Vendor Integration Protocol (a TDM bus standard)
Optical Carrier 3 - 155.52 Mbps leased line
Plesiochronous Digital Hierarchy
Phase Locked Loop
Primary Reference Source
Packet Receive
Zarlink Semiconductor Inc.
ZL50110/11/14
100
Data Sheet