ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 93

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

External Read/Write Address: 006C
Reset Value: 0002
15
15 - 3
0
2 - 0
External Read/Write Address: 0100
Reset Value: 0000
15 - 9
5 - 4
Bit
15
8 - 6
0
Bit
14
0
14
0
13
0
OJP2 - 0
STIN[n]SMP1 - 0
Unused
STIN[n]BD2 - 0
Name
13
H
H
0
12
0
Unused
Name
Table 61 - Stream Input Control Register 0 - 31 (SICR0 - 31) BIts
11
0
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Output Jitter Performance Bits: These bits are used to control the DPLL output jitter
performance with respect to the noise received through the output pins. The higher
value (unsigned) means more filtering, while zero means filter bypass. The default
value of 2
10
Table 60 - Output Jitter Control Register (OJCR) Bits
0
H
- 011F
11
H
0
0
9
H
Reserved
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
STIN[n]SMP1-0
H
STIN[n]
10
BD2
0
gives the best performance for most circumstances.
8
00
01
10
11
.
STIN[n]
9
0
In normal functional mode, these bits MUST be set to zero
Zarlink Semiconductor Inc.
BD1
7
ZL50018
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams)
8
0
STIN[n]
BD0
93
6
7
0
STIN[n]
SMP1
Description
Sampling Point
5
6
0
3/4 point
1/4 point
2/4 point
4/4 point
Description
STIN[n]
SMP0
4
5
0
:
STIN[n]
DR3
4
0
3
3
0
STIN[n]
DR2
2
OJP2
(16.384 Mbps streams)
2
STIN[n]
Sampling Point
DR1
1
2/4 point
4/4 point
OJP1
Data Sheet
1
.
STIN[n]
DR0
0
OJP0
0