ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 16

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

B7, C7, B5,
PBGA Pin
J6, D6, H5
G15, G14,
H14, D11
E15, F14
Number
F15
LQFP Pin
102, 106,
170, 172,
174, 227,
100, 104
176, 221
Number
110, 112
108
FPo_OFF0 - 1
FPo_OFF2
Pin Name
CKo0 - 5
FPo0 - 3
FPo5
or
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8kHz frame pulse corresponding to 4.096,
8.192, 16.384, or 32.768 MHz output clock of CKo3.
In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot
be narrower than the input frame pulse (FPi) width.
Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame
Pulse Output (5 V-Tolerant Three-state Output)
As FPo_OFF2, this is an individually programmable 8 kHz width
frame pulse, offset from the output frame boundary by a
programmable number of channels.
By programming the FP19EN (bit 10) of FPOFF2 register to high,
this signal becomes FPo5, a non-offset frame pulse corresponding
to the 19.44 MHz clock presented on CKo5. FPo5 is only available
in Master mode or when the SLV_DPLLEN bit in the Control
Register is set high while the device is in one of the slave modes.
ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096, 8.192, 16.384 or 32.768 MHz programmable output
clock;
CKo4: 1.544 or 2.048 MHz programmable output clock.
CKo5: 19.44 MHz output clock.
See Section 6.0 on page 24 for details. In Divided Slave mode, the
frequency of CKo0 - 3 cannot be higher than input clock (CKi).
CKo4 and CKo5 are only available in Master mode or when the
SLV_DPLLEN bit in the Control Register is set high while the
device is in one of the slave modes.
ZL50018
16
Description
Data Sheet