ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 89

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MML
External Read/Write Address: 006A
FML
Reset Value: 0000
External Read Only Address: 0069
15
R3
15
R3
Bit
Bit
15
14
13
12
4
3
2
1
0
MMU
FMU
14
R3
14
R3
Table 57 - Reference Failure Status Register (RSR) Bits - Read Only (continued)
R3MMU
R0FMU
R3MML
R0FML
R3MU
Name
Name
R1FU
R0FU
R3ML
R0FL
13
R3
ML
13
R3
FL
H
MU
12
R3
12
R3
FU
Reference 1 Single Period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF1 fails the single-period upper limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
Reference 0 Multi-period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF0 fails the multi-period lower limit check. (See Table 13, “Default Multi-period
Hysteresis Limits” on page 47)
Reference 0 Multi-period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF0 fails the multi-period upper limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 0 Single Period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF0 fails the single-period lower limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
Reference 0 Single Period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF0 fails the single-period upper limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
Reference 3 Multi-period Lower Limit Mask Bit: When this bit is high, it masks the
multi-period lower limit check (or forces pass) for REF3.
Reference 3 Multi-period Upper Limit Mask Bit: When this bit is high, it masks the
multi-period upper limit check (or forces pass) for REF3.
Reference 3 Single-period Lower Limit Mask Bit: When this bit is high, it masks the
single-period lower limit check (or forces pass) for REF3.
Reference 3 Single-period Upper Limit Mask Bit: When this bit is high, it masks the
single-period upper limit check (or forces pass) for REF3.
MML
H
FML
H
11
R2
Table 58 - Reference Mask Register (RMR) Bits
R2
11
MMU
FMU
10
R2
10
R2
ML
R2
R2
FL
9
9
Zarlink Semiconductor Inc.
ZL50018
MU
R2
FU
R2
8
8
89
MML
FML
R1
R1
7
7
Description
Description
MMU
FMU
R1
R1
6
6
ML
R1
R1
FL
5
5
MU
R1
R1
FU
4
4
MML
FML
R0
R0
3
3
MMU
FMU
R0
R0
2
2
Data Sheet
R0
ML
R0
FL
1
1
MU
R0
R0
FU
0
0