ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 38

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.1
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to
REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and
holdover functions. In this mode, STio0 - 31 are driven by a clock generated by the DPLL, which also provides all
the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2). One of the output clocks and frame
pulses should be looped back to CKi/FPi as reference for the input data, either by internal loopback (by setting the
CKi_LP bit high in the Control Register) or through some external loopback paths. If external loopback is used, it is
recommended that CKo2 (16.384MHz) and FPo2 (61ns pulse) are used so that all input data rates are available.
11.2
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same jitter characteristics as the input clock (CKi), but the input and output data rates cannot
exceed the limit defined by CKi (as per Table 1). For example, if CKi is 4.096 MHz, the input and output data rate
cannot be higher than 2.048 Mbps and the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is
not enabled, an external oscillator is optional in Divided Slave mode.
11.3
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are
driven by this internally generated clock. In this mode, the output clocks and data can run at any of the specified
rates, but they may have different jitter characteristics from the input clock (CKi). The input data rates are still
limited by the CKi rate (as per Table 1), as input data are always sampled directly by CKi. If the DPLL is not
enabled, an external oscillator is not required in Multiplied Slave mode.
12.0
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL
meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 3 compliant PLL.
This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover functions. The
intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output).
The input locking range of the DPLL is programmable, such that it can be larger than the strict Stratum 3
requirements.
The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL
module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
While in freerun mode, the DPLL is able to work in software mode which allows the user to program an output
frequency offset value through the microport of the device. Depending on the selected software mode, the DPLL
outputs can:
a. gradually meet the given frequency offset (following pre-programmed phase alignment speed (phase
b. immediately, upon finishing the microport write, reach the given frequency offset, allowing an external
slope) and internal filter response), or
filter to be used.
Master Mode Operation
Divided Slave Mode Operation
Multiplied Slave Mode Operation
Overall Operation of the DPLL
Zarlink Semiconductor Inc.
ZL50018
38
Data Sheet