ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 115
![no-image](/images/no-image-200.jpg)
ZL50018
Manufacturer Part Number
ZL50018
Description
2 K Digital Switch with Enhanced Stratum 3 DPLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50018.pdf
(136 pages)
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† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
1
2
(16.384 MHz)
STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
STi Hold Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Input Frame Boundary
(4.096 MHz)
(8.192 MHz)
2.048 Mbps
4.096 Mbps
8.192 Mbps
STi0 - 31
STi0 - 31
STi0 - 31
Figure 33 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps
CKi
CKi
FPi
CKi
FPi
FPi
Characteristic
Ch127
Bit1
Ch31
Bit0
Ch63
Bit0
Ch127
Bit0
†
- ST-BUS/GCI-Bus Input Timing
Ch0
Bit7
t
t
Sym.
SIS8
t
t
t
t
t
t
t
SIH16
SIS2
SIS4
SIS8
SIH2
SIH4
SIH8
SIS16
Ch0
Bit7
Ch0
Zarlink Semiconductor Inc.
Bit6
t
SIH8
t
SIS4
ZL50018
Min.
5
5
5
8
8
8
8
8
t
SIH4
Bit5
Ch0
115
Ch0
Bit7
Typ.
Ch0
Bit6
t
SIS2
Ch0
Bit4
t
SIH2
Max.
Bit3
Ch0
Units
Ch0
Bit5
ns
ns
ns
ns
ns
ns
ns
ns
Ch0
Bit2
Ch0
Bit1
Ch0
Bit6
Test Conditions
Ch0
Bit4
Ch0
Bit0
Data Sheet
V
V
V
V
CT
CT
CT
TT
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