ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 9

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.2
The most critical element of the ZL30402 is its Core PLL, which generates a phase-locked clock, filters jitter and
wander and suppresses input phase transients. All of these features are in agreement with international standards:
The Core PLL supports three mandatory modes of operation: Free-run, Normal (Locked) and Holdover. Each of
these modes places specific requirements on the building blocks of the Core PLL.
Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram".
Digitally Controlled Oscillator (DCO):
numbers that represent the phase-locked clock. These numbers are passed to the Clock Synthesizer (see
section 2.3) where they are converted into electrical clock signals of different frequencies.
Filters: In Normal mode, the clock generated by the DCO is phase-locked to the input reference signal and band-
limited to meet network synchronization standards. The ZL30402 provides two software programmable (Control
Reg 1) and two hardware selectable (FCS pin) filtering options. The filtering characteristics are similar to a first
order low pass filter with corner frequencies that support international standards:
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Core PLL
G.813 Option 1 and 2 clocks for SDH equipment
GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC)
GR-1244 for stratum 3 Clocks
In Free-run Mode, the Core PLL locks to the 20 MHz Master Clock Oscillator connected to pin C20i. The
stability of the generated clock remains the same as the stability of the Master Clock Oscillator but frequency
accuracy is greatly improved by the Master Clock Frequency Calibration register. This register compensates
oscillator frequency, practically eliminating manufacturing tolerances.
In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide
preprocessed phase data to the Core PLL including detection of reference clock quality. This preprocessing
reduces the load on the Core PLL and improves quality of the generated clock.
In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The
Core PLL enters Holdover mode if the attached Acquisition PLL switches into the Holdover state or under
external software or hardware control.
0.1 Hz filter: supports G.813 Option 2 Clock, GR-253 SONET stratum 3 and GR-253 SONET Minimum clock
1.1 Hz filter: supports G.813 Option 1 and GR-1244 stratum 3 clock
MUX
LOCK
RefAlign
Figure 3 - Core PLL Functional Block Diagram
Detector
FSM
Phase
The DCO is an arithmetic unit that continuously generates a stream of
Zarlink Semiconductor Inc.
ZL30402
9
Filters
FCS
DCO
Data Sheet