ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 22

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 14 H
Address: 19 H
7-3
Bit
2
1
0
7-5
Bit
4
3
2
1
0
AHRD
Name
MHR
RSV
RSV
F16odis
C19dis
F8odis
F0odis
Name
C6dis
RSV
Reserved.
Manual Holdover Release. A change form 0 to 1 on the MHR bit will release the Core
PLL from Auto Holdover to Normal when automatic return from Holdover is disabled
(AHRD is set to 1). This bit is level sensitive and it must be cleared immediately after it
is set to 1 (next write operation). This bit has no effect if AHRD is set to 0.
Automatic Holdover Return Disable. When set high, this bit inhibits the Core PLL
from automatically switching back to Normal mode from Auto Holdover state when the
active Acquisition PLL regains lock to input reference. The active Acquisition PLL is the
Acquisition PLL to which the Core PLL is currently connected.
Reserved.
Reserved.
F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns
active high framing pulse output.
F0o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 244 ns
active low framing pulse output.
F16o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 61 ns
active low framing pulse output.
6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz clock
output.
19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz clock
output.
Table 14 - Core PLL Control Register (R/W)
Table 13 - Clock Disable Register 2 (R/W)
Zarlink Semiconductor Inc.
Functional Description
Functional Description
ZL30402
22
Data Sheet
Default
Default
00000
000
0
0
0
0
0
0
0
0