ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 25

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 43 H
5.0
This section contains application specific details for Mode Switching and Master Clock Oscillator calibration.
5.1
The ZL30402 is designed to transition from one mode to the other driven by the internal State Machine or by
manual control. The following examples present a couple of typical scenarios of how the ZL30402 can be employed
in network synchronization equipment (e.g., timing modules, line cards or stand alone synchronizers).
5.1.1
The FREE-RUN to HOLDOVER to NORMAL transition represents a sequence of steps that will most likely occur
during a new system installation or scheduled maintenance of timing cards. The process starts from the RESET
state and then transitions to Free-run mode where the system (card) is being initialized. At the end of this process
the ZL30402 should be switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the
reference clock is available, the ZL30402 will transition briefly into Holdover to acquire synchronization and switch
automatically to Normal mode. If the reference clock is not available at this time, as it may happen during new
system installation, then the ZL30402 will stay in Holdover indefinitely. While in Holdover mode, the Core PLL will
continue generating clocks with the same accuracy as in the Free-run mode, waiting for a good reference clock.
When the system is connected to the network (or timing card switched to a valid reference) the Acquisition PLL will
quickly synchronize and clear its own Holdover status (PAH bit). This will enable the Core PLL to start the
synchronization process. After acquiring lock, the ZL30402 will automatically switch from Holdover into Normal
mode without system intervention. This transition to the Normal mode will be flagged by the LOCK status bit and
pin.
7-0
Bit
ZL30402 Mode Switching - Examples
Applications
RESET
System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL
RESET == 1
unconditional return from
MCFC7 - 0
MS2, MS1 == 10 forces
any state to Free-run
Name
Table 21 - Master Clock Frequency Calibration Register 1 (R/W)
FREE-
RUN
10
MS2, MS1! = 10
Figure 7 - Transition from Free-Run to Normal Mode
Master Clock Frequency Calibration. This byte contains bit 7 to
bit 0 of the Master Clock Frequency Calibration Register.
MS2, MS1 == 01 OR
RefSel change
HOLD-
OVER
01
Zarlink Semiconductor Inc.
MS2, MS1 == 00
ZL30402
Ref: OK &
{AUTO}
Functional Description
25
RefSel Change
(LOCKED)
NORMAL
00
Ref: OK --> FAIL &
MS2, MS1 == 00
{AUTO}
HOLD-
AUTO
OVER
MHR= 0 -->1 then 1-->0
{MANUAL}
AHRD=0
{AUTO}
MS2, MS1 == 00 &
Ref: FAIL --> OK &
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=1 &
Data Sheet
Default
00000
000