ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet
ZL30402/QCC
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ZL30402/QCC Summary of contents
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... DS R/W Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Network Element PLL ZL30402/QCC ZL30402QCC1 Description The ZL30402 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST-BUS and GCI backplanes ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ZL30402 Pinout 1.1 Pin Connections RESET GND IC IC VDD R Figure 2 - Pin Connections for 80-pin LQFP package ZL30402 ...
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Pin Description Pin # Name 1 IC 2-5 A1-A4 6 GND 7-8 A5-A6 9 FCS 10 VDD 11 GND 12 F16o 13 C16o 14 C8o 15 C4o 16 C2o 17 F0o 18 MS1 19 MS2 ZL30402 Description Internal Connection. Leave ...
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Pin Description (continued) Pin # Name 20 F8o 21 E3DS3/OC3 22 E3/DS3 23 SEC 24 PRI 25 GND GND 28 AVDD 29 VDD 30 C155N 31 C155P 32 GND Tdo ZL30402 Description Frame Pulse ...
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Pin Description (continued) Pin # Name 35 Tms 36 Tclk 37 Trst 38 Tdi C1.5o 43 C6o GND 46 C19o 47 RefSel 48 RefAlign 49 VDD C20i ...
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Pin Description (continued) Pin # Name 53 C34/C44 54 VDD 55 HOLDOVER LOCK RESET 65 HW 66- GND 71 IC ...
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Pin Description (continued) Pin # Name R 2.0 Functional Description The ZL30402 is a Network Element PLL designed to provide timing for SDH and SONET equipment conforming to ITU-T, ...
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Core PLL The most critical element of the ZL30402 is its Core PLL, which generates a phase-locked clock, filters jitter and wander and suppresses input phase transients. All of these features are in agreement with international standards: - G.813 ...
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Lock Indicator: Entry into Normal mode is flagged by the LOCK status bit or pin. Lock is declared when the Acquisition PLL is locked to the reference clock and the Core PLL is locked to the Acquisition PLL. Frequency lock ...
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C155 Output C155 Output E3DS3/OC3 0 1 155.52 HIZ Figure 4 - C19o, C155o, C34/C44 Clock Generation Options All clocks and frame pulses except the C155 are output with CMOS logic levels. The C155 clock (155.52MHz) is output in a ...
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MS2, MS1 == 01 OR RefSel change MS2, MS1 RESET == 1 FREE- RESET RUN 10 MS2, MS1 == 10 forces unconditional return from any state to Free-run Notes: ==: equal ! =: not equal & =: AND ...
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Holdover State (Holdover Mode) The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30402 generates clocks, which are not locked to an external reference signal but their frequencies are ...
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The compensation value for the Master Clock Calibration Register (MCFC3 to MCFC0) can be calculated from the following equation: MCFC = 45036 * ( - f ) where: offset The f frequency should only be measured after the Master Crystal ...
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Pins MS2 MS1 FCS RefSel RefAlign LOCK HOLDOVER Figure 6 - Hardware and Software Control options 4.1 Hardware Control The Hardware control is a subset of software control and it will only be briefly described with cross-referencing to Software control ...
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FCS 0 Filter corner frequency set to 1.1 Hz. This selection meets requirements of G.813 Option 1 and GR-1244 stratum 3 clocks. 1 Filter corner frequency set to 0.1 Hz. This selection meets requirements of G.813 Option 2, GR-253 for ...
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Status Bits The ZL30402 has seven status bits (see Figure 6 "Hardware and Software Control options"). The first two bits perform the same function as their equivalent status pins. The last five bits perform two functions. Bits FLIM, PAFL, ...
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Register Description Address Bit Name 7 RefSel Reference Select. A zero selects the PRI (Primary) reference source as the input reference signal and a one selects the SEC (secondary) reference. 6-5 RSV Reserved. 4-3 MS2, MS1 Mode ...
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Address Bit Name 7 RSV Reserved. 6 RSV Reserved. 5 LOCK Lock. This bit goes high when the Core PLL is locked to the selected Acquisition PLL. 4 HOLDOVER Holdover. This bit goes high when the Core PLL ...
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Address Bit Name 7-4 RSV Reserved. 3 OffEn Offset Enable. Set high to enable programmable phase offset adjustments (C16 Phase Offset Adjustment and C1.5 Phase Offset Adjustment) between the input reference and the generated clocks ...
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Address Bit Name 7 RSV Reserved. 6 RSV Reserved. 5-3 C1.5POA2 C1.5 Phase Offset Adjustment. These three bits allow for changing of to the phase offset of the C1.5o clock relative to the active input reference. C1.5POA0 The ...
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Address Bit Name 7-5 RSV Reserved. 4 F8odis F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns active high framing pulse output. 3 F0odis F0o Frame Pulse Disable. When set high, this ...
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Address Bit Name 7-0 FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset adjustment of all output clocks and frame pulses (C16o, C8o, C4o, C2o, F16o, F8o, F0o, C155, C19o, C34/44, C1.5o, C6o) relative to ...
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Address Bit Name 7-5 RSV Reserved. 4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency 19.44 MHz - kHz - 10 = 1.544 MHz - 11 = 2.048 ...
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Address Bit Name 7-0 MCFC7 - 0 Master Clock Frequency Calibration. This byte contains bit 7 to bit 0 of the Master Clock Frequency Calibration Register. Table 21 - Master Clock Frequency Calibration Register 1 (R/W) 5.0 Applications ...
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Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses its single reference clock unexpectedly or when it has two references but switching to the ...
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Dual Reference Operation: The NORMAL to AUTO-HOLDOVER to HOLDOVER to NORMAL sequence represents the most likely operation of ZL30402 in Network Equipment. The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen ...
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Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL The NORMAL to HOLDOVER to NORMAL mode switching is usually performed when: • A reference clock is available but its frequency drifts beyond some specified limit Network Element with ...
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Example 1: Calculate the binary value that must be written to the MCFC register to correct a -1ppm offset of the Master Crystal Oscillator. The -1ppm offset for a 20 MHz frequency is equivalent to -20 Hz: MCFC = 45036 ...
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DC Electrical Characteristics* Characteristics 1 Supply current with C20i = 20 MHz 2 Supply current with C20i = 0V 3 CMOS high-level input voltage 4 CMOS low-level input voltage 5 Input leakage current 6 High-level output voltage 7 Low-level output ...
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AC Electrical Characteristics - Microprocessor Timing* Characteristics 1 DS Low 2 DS High 3 CS Setup 4 CS-Hold 5 R/W Setup 6 R/W Hold 7 Address Setup 8 Address Hold 9 Data Read Delay 10 Data Read Hold 11 Data ...
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AC Electrical Characteristics - ST-BUS and GCI Output Timing* Characteristics 1 F16o pulse width low (nom 61ns) 2 F8o to F16o delay 3 C16o pulse width low 4 C16o to F8o delay 5 F8o pulse width high (nom 122 ns) ...
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AC Electrical Characteristics - DS1, DS2 and C19o Clock Timing* Characteristics 1 C6o pulse width low 2 F8o to C6o delay 3 C1.5o pulse width low 4 C1.5o to F8o delay 5 C19o pulse width high 6 C19o to F8o ...
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AC Electrical Characteristics - C155o and C19o Clock Timing Characteristics 1 C155o pulse width low 2 C155o to C19o rising edge delay 3 C155o to C19o falling edge delay 4 C19 pulse width high * Supply voltage and operating temperature ...
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AC Electrical Characteristics - Input to Output Phase Alignment (after RefAlign change from 1 to 0)* Characteristics 1 8 kHz ref pulse width high 2 F8o to 8 kHz ref input delay 3 1.544 MHz ref pulse width high 4 ...
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AC Electrical Characteristics - Input Control Signals* Characteristics 1 Input controls Setup time 2 Input controls Hold time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8o t S MS1, MS2 RefSel, FCS, RefAlign E3/DS3, E3DS3/OC3 ...
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Performance Characteristics Performance Characteristics* Characteristics 1 Holdover accuracy 2 Holdover stability 3 Capture range Lock time 4 1.1Hz Filter 5 0.1Hz Filter Output Phase variation 6 Reference switching: PRI ⇐ SEC, SEC ⇐ PRI 7 Switching from Normal mode ...
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Performance Characteristics - Jitter Generation (Intrinsic Jitter) - Filtered* Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C19o (19.44 MHz) Dejittered 4 C19o (19.44 MHz) Dejittered 5 C19o (19.44 MHz) Dejittered 6 C19o (19.44 MHz) Dejittered 7 C19o ...
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Performance Characteristics - Jitter Generation (Intrinsic Jitter) - Unfiltered* Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C4o- (4.096 MHz) 4 C6o (6.312 MHz) 5 C8o (8.192 MHz) 6 C8.5o (8.592 MHz) 7 C11o (11.184 MHz) 8 C16o- ...
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