ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 6

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
RefAlign
RefSel
Name
C1.5o
C19o
GND
GND
VDD
C20i
Tms
C6o
Tclk
Trst
Tdi
NC
NC
NC
IC
IC
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
IEEE1149.1a Test Clock Signal (5.5 V tolerant input). Input clock for the
JTAG test logic. If not used, this pin should be pulled up to VDD.
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG
TAP controller. This pin should be pulsed low on power-up to ensure that the
device in the normal functional state. This pin is internally pulled up to VDD. If
not used, this pin should be connected to GND.
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test
instructions and data. This pin is internally pulled up to VDD. If not used, this
pin should be left unconnected.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz
DS1 rate clock.
Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz
DS2 rate clock.
Internal Connection. Connect this pin to Ground.
Ground.
Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz
clock.
Reference Source Select (Input). A logic low selects the PRI (primary)
reference source as the input reference signal and logic high selects the SEC
(secondary) input. The logic level at this input is sampled at the rising edge of
F8o. This pin is internally pulled down to GND.
Reference Align (Input). In Hardware Control a high to low transition at this
input initiates phase realignment between the input reference and the
generated output clocks. This pin is internally pulled down to GND.
Positive Power Supply.
No internal bonding Connection. Leave unconnected.
Clock 20 MHz (5.5 V tolerant input). This pin is the input for the 20 MHz
Master Clock Oscillator.
Digital Ground.
Zarlink Semiconductor Inc.
ZL30402
6
Description
Data Sheet