AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 71

• Manufacturer Part Number: AK4646EN
• Description: Stereo CODEC with MIC/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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MS0557-E-02
(Addr:05H, D5&D2-0)
(Addr:00H&10H, D0)
ALC Control 4
ALC Control 1
ALC Control 2
ALC Control 3
(Addr:02H, D2-0)
ADC Internal
MIC Control
MIC Input Recording (Stereo)
PMADL/R bit
<Example>
ALC State
FS3-0 bits
(Addr:0BH)
(Addr:07H)
(Addr:06H)
(Addr:08H)
This sequence is an example of ALC setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Figure 29. Registers set-up sequence at ALC operation”
State
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK4646 is PLL mode, MIC and ADC should be powered-up
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC (Addr: 06H)
(4) Set up IREF value for ALC (Addr: 08H)
(5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1”
(8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0”
(9) ALC Disable: ALC bit = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK4646 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADC or PMADR
bit is changed to “1”.
in consideration of PLL lock time after a sampling frequency is changed.
The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (+30dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog
input pin going to the common voltage and the constant time of the offset cancel digital HPF. This time can be
shorter by using the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The waiting time to
power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling
capacitor at analog input pin and the internal input resistance 30k(typ).
0,000
00H
E1H
28H
00H
001
(1)
ALC Disable
Power Down
(2)
(3)
(4)
(5)
(6)
Figure 42. MIC Input Recording Sequence
(7)
Initialize Normal State Power Down
1059 / fs
ALC Enable
1,111
3CH
E1H
28H
101
21H
- 71 -
(8)
ALC Disable
(9)
01H
Example:
Audio I/F Format:MSB justified (ADC & DAC)
Pre MIC AMP:+20dB
Sampling Frequency:44.1KHz
MIC Power On
PLL Master Mode
ALC setting:Refer to Figrure 23
(1) Addr:05H, Data:27H
(3) Addr:06H, Data:3CH
(4) Addr:08H, Data:E1H
ALC1 bit=“1”
(2) Addr:02H, Data:05H
(5) Addr:0BH, Data:28H
(6) Addr:07H, Data:21H
(7) Addr:00H, Data:41H
(8) Addr:00H, Data:40H
(9) Addr:07H, Data:01H
Addr:10H, Data:01H
Addr:10H, Data:00H
Recording
[AK4646]
2007/05