AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 55

• Manufacturer Part Number: AK4646EN
• Description: Stereo CODEC with MIC/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

■
MS0557-E-02
Addr
00H
Register Definitions
PMADL: MIC-Amp Lch and ADC Lch Power Management
PMDAC: DAC Power Management
PMLO: Stereo Line Out Power Management
PMSPK: Speaker-Amp Power Management
PMBP: MIN Input Power Management
PMVCM: VCOM Power Management
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H and 10H addresses and MCKO bit is “0”, all blocks are
powered-down. The register values remain unchanged.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
0: Power-down (default)
1: Power-up
Register Name
Power Management 1
Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL
or BEEPS bit is used to control each path when MIN input is used.
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H,02H, 10H and MCKO bits are “0”.
Default
R/W
D7
R
0
0
PMVCM
R/W
D6
0
PMBP
- 55 -
R/W
D5
0
PMSPK
R/W
D4
0
PMLO
R/W
D3
0
PMDAC
R/W
D2
0
D1
R
0
0
[AK4646]
PMADL
2007/05
R/W
D0
0