AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 42

• Manufacturer Part Number: AK4646EN
• Description: Stereo CODEC with MIC/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
MS0557-E-02
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
WR (ZTM1-0, WTM2-0, RFST1-0)
Comment
Limiter detection Level
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
Maximum gain at recovery operation
Gain of VOL
Limiter ATT step
Fast Limiter Operation
Recovery GAIN step
Fast Recovery Speed
ALC enable
Limiter zero crossing detection
WR (RGAIN1, LMTH1)
as ZTM1-0 bits
Note : WR : Write
WR (IVL/R7-0)
WR (IREF7-0)
ALC Operation
Manual Mode
Figure 29. Registers set-up sequence at ALC operation
Table 33. Example of the ALC Setting (Playback)
* The value of IVOL should be
the same or smaller than REF’s
- 42 -
Data
28H
91H
001
01
01
00
00
00
0
1
1
fs=8kHz
Example:
− 4.1dBFS
Operation
4 times
Enable
Enable
1 step
1 step
+6dB
32ms
32ms
0dB
ON
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
(3) Addr=09H&0CH, Data=E1H
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=21H
Data
28H
91H
100
01
00
00
11
00
0
1
1
fs=44.1kHz
Operation
− 4.1dBFS
23.2ms
46.4ms
4 times
Enable
Enable
1 step
1 step
+6dB
0dB
ON
[AK4646]
2007/05