AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 20

• Manufacturer Part Number: AK4646EN
• Description: Stereo CODEC with MIC/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4646 is supplied stable clocks after PLL is
powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency is changed.
1) Setting of PLL Mode
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (Table 6).
MS0557-E-02
Others
Mode
PLL Mode
12
13
0
1
2
3
6
7
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
Others
Mode
PLL3
Others
Mode
bit
0
1
2
10
11
14
15
0
0
0
0
0
0
1
1
0
1
2
3
4
5
6
7
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
Others
PLL2
bit
0
0
0
0
1
1
1
1
FS3 bit
FS3 bit
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
PLL1
bit
0
0
1
1
1
1
0
0
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
FS2 bit
PLL0
0
1
0
bit
(PLL Reference: Clock: LRCK or BICK pin)
0
1
0
1
0
1
0
1
FS2 bit
0
0
0
0
1
1
1
1
0
0
1
1
Others
Clock Input
Others
LRCK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
Reference
Don’t care
Don’t care
Don’t care
BICK pin
BICK pin
FS1 bit
PLL
N/A
N/A
Pin
FS1 bit
0
0
1
1
0
0
1
1
1
1
1
1
- 20 -
Don’t care
Don’t care
Don’t care
FS0 bit
Frequency
13.5MHz
12MHz
24MHz
27MHz
Input
32fs
64fs
FS0 bit
1fs
-
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
7.35kHz ≤ fs ≤ 12kHz
Sampling Frequency
R[Ω]
6.8k
10k
10k
10k
10k
10k
10k
10k
10k
R and C of
VCOC pin
-
Range
11.025kHz
22.05kHz
N/A
7.35kHz
14.7kHz
29.4kHz
44.1kHz
12kHz
16kHz
24kHz
32kHz
48kHz
8kHz
N/A
220n
C[F]
4.7n
4.7n
10n
10n
10n
10n
10n
10n
-
PLL Lock
160ms
(max)
40ms
40ms
40ms
40ms
Time
2ms
4ms
2ms
4ms
-
(default)
(default)
[AK4646]
(default)
2007/05