AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 52
AK4646EN
Manufacturer Part Number
AK4646EN
Description
Stereo CODEC with MIC/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4646EN.pdf
(79 pages)
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Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (“ ↑ ”) of CCLK. It is available for writing data on the rising edge of CSN. When reading
operation, CDTIO pin has become an output mode at the falling edge of 8
finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state except outputting data at read operation mode.
Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”.
Note 38. It is available for reading the address 00H~11H. When reading the address 12H ∼ 7FH, the register values are
MS0557-E-02
invalid.
Serial Control Interface
CDTIO
CSN
CCLK
“H” or “L”
“H” or “L”
R/W:
A6-A0:
D7-D0: Control data (Input) at Write Command
A6 A5
0
1
R/W
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Output data (Output) at Read Command
2
Figure 36. Serial Control I/F Timing
A4
3
A3
4
A2
5
A1 A0
6
- 52 -
7
D7 D6 D5 D4 D3 D2 D1 D0
8
9
10 11 12 13 14 15
th
CCLIC and outputs D7-D0. The output
“H” or “L”
“H” or “L”
[AK4646]
2007/05
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